With the rapid development of semiconductor technology, the feature size of semiconductor structures is continuously reduced, and the integration level of integrated circuits (ICs) becomes higher and higher. Accordingly, the requirements on the performance of the devices may be higher.
Currently, with the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) continuously becoming smaller, the channel length in MOSFET devices may have to be reduced in order to accommodate the reduction of the process node. The reduction of the channel length, may be conducive to increasing the density of transistors in the chip, improving the switching speed of the MOSFET devices.
However, as the channel length of devices decreases, the distance between the source and the drain of the devices may also be reduced. As a result, the ability of the gate structure in con trolling the channel may be degraded, and thus pinching off the channel by the gate may be more and more difficult. Therefore, the sub-threshold leakage phenomenon, e.g., the short-channel effect (SCE), becomes a crucial technical challenge and needs to be resolved.
In order to accommodate the requirements for scaling-down semiconductor devices, semiconductor process gradually switches from planar MOSFET devices to more efficient three-dimensional (3D) transistor devices, such as fin field-effect transistor (Fin-FET) devices, which demonstrate desired ability in controlling the channels.
However, the electrical performance of the conventional semiconductor structures may still need to be improved. The disclosed semiconductor devices and fabrication methods are directed to solve one or more problems set forth above and other problems in the art.